During various integrated circuit (IC) fabrication steps, numerous layers are deposited onto lower layers which may have previously defined lithographic features such as trenches and holes formed therein. These deposited films often show a conforming surface to the topography of the underlying trenches and holes, as the deposited layers fill in these features. Therefore, a non-uniform surface with various dimple areas and depths will form as a result of the trench and hole features. A non-uniform film surface can interfere with subsequent IC fabrication steps such as photolithography, film depositions and film removals, and can cause yield loss from non-functional devices. Planarization of non-uniform surfaces is therefore a critical step in IC manufacturing.
For example, it is often desired to form an electrical connection to a conductive layer lying underneath an insulating dielectric layer. These connections are made by lithographically patterning a set of holes, or vias, through the dielectric layer to the conducting layer, and depositing a conductive material, for example polysilicon, in the holes. The excess conductive material can then be removed from the surface of the dielectric layer by an etch back process, leaving the conductive material only in the vias, and not on the surrounding surface.
It is an ongoing challenge for etch back processes to remove the conductive material thoroughly, while leaving a smooth, planar surface, with little or no surface topography in the vicinity of the vias. A figure of merit for an etch back process is the reduction of the recess height, which is the height differential between the planar surface and the top of the polysilicon plug filling the vias. In general, a recess height of less than 30 nm is specified for IC processes.
Achieving a planar surface after deposition is therefore a primary goal of etch back processes, processes used to remove a portion of a previously deposited material. Traditionally, a substantially planar surface is achieved by chemical mechanical polishing (CMP) tools or a high density plasma etcher. CMP is an abrasive process, in which material is removed by applying a rotating pad under pressure against the substrate, in the presence of an abrasive compound or slurry. The slurry is chosen to selectively remove one film over another. While CMP enjoys widespread use in the IC industry, it is expensive, and requires frequent operator maintenance to replace the pads or handle the slurry. The process is also slow, requiring long process times, which increases the cost of ownership of the tool. Lastly, most CMP slurry removes the polysilicon material preferentially to the oxide, and therefore leaves recesses at the sites of the polysilicon plugs. CMP typically produces wafers that have a recess height in excess of about 30 nm.
Alternatively, an ion etcher can be used to remove a top layer of polysilicon. However the ion etchers also tend to leave topography over the dimple areas, as the charged species are attracted to the corners of the topography because of the high fields existing there. Therefore, typical plasma etchers tend to accentuate already existing contours, and are not very effective at planarizing contoured areas remaining near lithographically patterned features.
The development of a high throughput advanced thin film removal or etch back process is desirable. A method for the rapid removal of the bulk polysilicon film, which leaves a flat surface topography and very little recess height, is also desirable.